1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly relates to a semiconductor device having a sense amplifier.
2. Description of Related Art
A memory such as a DRAM is known which includes an internal power supply of a voltage lower than a voltage of an external power supply and uses the internal power supply as a power supply for a memory cell in accordance with a smaller power consumption and a higher speed operation. FIG. 1 is a circuit diagram showing a typical configuration of a sense amplifier in such a DRAM. The sense amplifier is connected to bit lines Bit and Bit/, and a wiring SAP to supply the voltage of the internal power supply, and a wiring SAN to supply a ground voltage. The power supply voltage of the sense amplifier supplied from the wiring SAP, namely, the voltage of a high level of the bit line Bit (Bit/) is used as the voltage of the internal power supply. Thus, it is possible to suppress the power that is consumed when the bit lines are driven at the time of a read operation.
FIG. 2 is a graph showing the time dependences of the voltages of PMOS transistors and the bit lines in the sense amplifier. The vertical axis indicates the drain voltages of the PMOS transistors and the voltage of the bit lines, and the horizontal axis indicates time. Curves E and F indicate the changes in the drain voltages of PMOS transistors Tr12 and Tr14, and curves G and H indicate the changes in the voltages of the bit lines Bit and Bit/.
When a power supply voltage VDD supplied to the sense amplifier is set to a low voltage, a delay is generated in the operation of the sense amplifier. That is, the sense amplifier does not substantially amplify a small voltage difference between the bit lines Bit and Bit/ approximately until a time tc, after its operation is started at a time ta, as shown by the curves G and H. The reason of the delay is in that since the power supply voltage VDD applied to a sense amplifier 103 is not sufficiently high as compared with the total of threshold voltages Vth of the PMOS transistor Tr12 (Tr14) and an NMOS transistor Tr13 (Tr11), the switching performance of the transistor is insufficient, and the voltages of the bit lines Bit and Bit/ cannot be quickly amplified.
Specifically, the source voltage of the PMOS transistor Tr12 (Tr14) rises up immediately after the sense amplifier starts the operation at the time ta (the curve E). However, when the voltage of the bit line Bit (Bit/) is slightly increased (near the time tb, curve G), the driving performance of the power supply voltage VDD is not sufficiently high, and the response is delayed, which temporally reduces the source voltage of the PMOS transistor Tr12 (Tr14) (near the time tb: curve E). As a result, the increase in the voltage of the bit line Bit (Bit/) is becomes slow, and it does not sharply rise up (near the time tb: curve G), which leads to the delay of the sense amplifier. When the voltage difference between the bit lines Bit and Bit/ arrives at a certain value, the amplification feedback in the circuit is rapidly applied, which rapidly increases the voltage difference (near the time tc: curve G).
Thus, when the voltage of this internal power supply is low, the sensibility of the sense amplifier to the increase or decrease of the power supply voltage (source voltage) of the sense amplifier becomes very high. As a result, this has an adverse influence on the high-speed operation of the sense amplifier. An over-drive method is known as a method to improve such a state. By using the over-drive method, a sufficient current supply capability can be attained. Therefore, the decrease in the source voltage of the PMOS transistor Tr12 (Tr14) can be suppressed, which provides the great effect of the higher speed.
As a related art, Japanese Patent Application Publication (JP-P2000-285676A) discloses a memory device having a sense amplifier of an over-drive method. This memory device contains a first power supply; a second power supply for a voltage lower than a voltage of the first power supply; and the sense amplifier that is connected through bit lines to a memory cell and amplifies voltages on the bit lines. The memory device further contains a sense amplifier control circuit that supplies the voltage of the first power supply to the sense amplifier during a first period when the sense amplifier is activated, and then supplies the second power supply voltage during a second period. The sense amplifier control circuit has a monitoring sense amplifier for amplifying a dummy bit line at a timing approximately simultaneous with the activation of the sense amplifier. The sense amplifier control circuit carries out the switching from the first power supply voltage to the second power supply voltage in accordance with the voltage of the dummy bit line, when the sense amplifier is activated.
Japanese Patent Application Publication (JP-A-Heisei, 11-121717) discloses a semiconductor memory device. This semiconductor memory device contains a plurality of unit amplifiers that are selectively made active when a predetermined drive voltage is supplied to a common source line; and a plurality of sense amplifiers which are dispersedly arranged on a semiconductor substrate and each of which has a drive MOSFET that is selectively turned on in response to a predetermined drive control signal and selectively transfers the drive voltage to the common source line. In this semiconductor memory device, a wiring width of the common source line or the gate width or gate length of the drive MOSFET is changed in accordance with the arrangement distance from the supply node of the drive voltage of the sense amplifier.
Japanese Patent Application Publication (JP-A-Heisei, 11-39875) discloses a semiconductor memory device. This semiconductor memory device contains first, second and third voltage supply nodes; a memory cell array; a sense amplifier block; first, second and third wirings; and a sense amplifier drive control section. A first voltage, a second voltage higher than the first voltage, and a third voltage higher than the second voltage are supplied from the first, second and third voltage supply nodes. In the memory cell array, a memory cell is arranged at a intersection point between a word line and a bit line pair to hold charges corresponding to the first or second voltage as a data. The sense amplifier block includes a sense amplifier, which is connected to the bit line pair and operates in response to the first and third voltages during a first period when the data held in the memory cell is read and operates in response to the first and second voltages during a second period. The first, second and third wirings are connected to the voltage supply nodes and supply the first voltage, the second voltage and the third voltage to the sense amplifier block, respectively. The sense amplifier drive control section adjusts the lengths of the first and second periods in accordance with the wiring lengths between the voltage supply nodes of the wirings and the sense amplifier block.
FIG. 3 is a graph showing time dependence of the drain voltages of the PMOS transistors in the sense amplifier of the over-drive method. This is based on a simulation. The vertical axis indicates the drain voltages of the PMOS transistors Tr12 and Tr14, and the horizontal axis indicates time. Curves A1 and A2, B1 and B2, C1 and C2, and D1 and D2 indicate cases of no over-drive execution, tA-time over-drive execution, a tB-time over-drive execution and a tC-time over-drive execution (tA<tB<tC), respectively. Also, FIG. 4 is a graph showing time dependence of the voltages of the bit lines in the sense amplifier of the over-drive method. This is based on a simulation. The vertical axis indicates the voltages of the bit lines Bit and Bit/, and the horizontal axis indicates time. Curves A3 and A4, B3 and B4, C3 and C4, and D3 and D4 indicate cases of no over-drive execution, tA-time over-drive execution, tB-time over-drive execution and tC-time over-drive execution (tA<tB<tC), respectively.
As shown in FIG. 4, the optimal execution time of the over-drive is the tC time (the curves C1 to C4). When the over-drive is excessive so that the source voltage is over-shot (the curve D1), the bit line voltage is also over-shot (the curve D3), so that there is a possibility that the high level of the bit line Bit (Bit/) is higher than the power supply voltage VDD. In that case, when the bit lines Bit and Bit/ are shorted after the read operation, the voltages of the bit lines Bit and Bit/ become higher than (½)VDD, so that pre-charge to (½)VDD cannot be attained. On the contrary, when the over-drive is lack (the curves B1, B3), the operation speed of the sense amplifier is made slow. Thus, the over-drive is required to be controlled.
With regard to it, the inventor of the present invention newly discovered the following technical aspects. In particular, as mentioned above, when the power supply voltage VDD is a low voltage, the sensibility of the sense amplifier to the source voltage of the PMOS transistor is very high, so that the optimal timing range is very narrow. In such a case, it is also important to consider any influence caused by the variations in element performances associated with the manufacture variations in elements such as transistors and the like. Here, the above Japanese Patent Application Publication (JP-P2000-285676A) discloses an over-drive sense amplifier control circuit for carrying out the timing control of the over-drive operation to the sense amplifier. However, only one over-drive sense amplifier control circuit is provided in the entire memory core. Thus, it is difficult to cope with the influence caused by the variations in the element performances. In addition, the over-drive sense amplifier control circuit is complex and occupies a relatively large area. This is because the dummy sense amplifier array is formed from the sense amplifier and circuits around the sense amplifier such as a dummy bit line, and a dummy pre-charging circuit. In other words, it is not practical from view of a chip penalty, and the electric power consumption that a plurality of dummy arrays are arranged in the memory core. Therefore, a technique is demanded which can control the over-drive at a high precision for each sense amplifier. Also, a technique is demanded which can control the over-drive at a high precision for the variation in element performances.